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CY29775
2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
Features

Description
The CY29775 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29775 features two reference clock inputs and provides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A and Bank B divide the VCO output by 4 or 8 while Bank C divides by 8 or 12 per SEL(A:C) settings, see Function Table (Bank A, B, and C) on page 4. These dividers allow output to input ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible output can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:28. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 8.3 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Frequency Table on page 4. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.
Output frequency range: 8.3 MHz to 200 MHz Input frequency range: 4.2 MHz to 125 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 14 Clock outputs: Drive up to 28 clock lines 1 Feedback clock output 2 LVCMOS reference clock inputs 150 ps max output-output skew PLL bypass mode Spread AwareTM Output enable/disable Industrial temperature range: -40C to +85C 52-Pin 1.0-mm TQFP package
Block Diagram
V C O _S E L(1,0) P LL_E N TCLK_SEL T C LK 0 TC LK1 F B _IN PLL 200 5 0 0M H z
/2 /4 /2 / /4 C LK STOP
S E LA
/2 / /4 C LK STOP
Q A0 Q A1 Q A2 Q A3 Q A4 QB0 QB1 Q B2 Q B3 QB4 QC0 QC1 QC2 QC3
S E LB
/4 / /6
C LK STOP
SELC C LK _S T P #
/4 / /6 / / 8 / / 12
F B _O U T
F B _S E L(1,0) M R #/O E
Cypress Semiconductor Corporation Document #: 38-07480 Rev. *A
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised December 19, 2007
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CY29775
Pinouts
Figure 1. Pin Diagram - 52-Pin 1.0-mm TQFP package
VCO_SEL0 QC1 VDDQC VSS QC3 VDDQC VDDQB NC
52 51 50 49 48 47 46 45 44 43 42 41 40 V SS MR#/OE CLK_STP# SELB SELC PLL_EN SELA TCLK_SEL TCLK0 TCLK1 V CO_SEL1 V DD A V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 V SS QB1 V DDQB QB2 V SS QB3 V DDQB QB4 FB_IN V SS FB_OUT V DDFB NC
14 15 16 17 18 19 20 21 22 23 24 25 26 FB_SEL0 QA4 AVSS QA3 VDDQA FB_SEL1 VSS QA1 VDDQA QA2 QA0 VSS VDDQA
Table 1. Pin Definition - 52-Pin 1.0-mm TQFP package Pin[1] 9 10 16, 18, 21, 23, 25 32, 34, 36, 38, 40 44, 46, 48, 50 29 31 Name TCLK0 TCLK1 QA(4:0) QB(4:0) QC(3:0) FB_OUT FB_IN IO I, PD I, PU O O O O I, PU Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Description LVCMOS/LVTTL reference clock input LVCMOS/LVTTL reference clock input Clock output bank A Clock output bank B Clock output bank C Feedback clock output. Connect to FB_IN for normal operation. Feedback clock input. Connect to FB_OUT for normal operation. This input must be at the same voltage rail as input reference clock. See Table 2 on page 4. Output enable/disable input. See Table 3 on page 4. Clock stop enable/disable input. See Table 3 on page 4. PLL enable/disable input. See Table 3 on page 4. Reference select input. See Table 3 on page 4. VCO divider select input. See Tables 3, 4 and 5. Frequency select input, Bank (A:C). See Table 4 on page 4. Feedback dividers select inputs. See Table 5 on page 5. 2.5V or 3.3V Power supply for bank A output clocks[2,3] 2.5V or 3.3V Power supply for bank B output clocks[2,3]
QC0 VSS
CY29775
QC2 VSS
QB0
2 3 6 8 11, 52 7, 4, 5 20, 14 17, 22, 26 33, 37, 41
MR#/OE CLK_STP# PLL_EN TCLK_SEL VCO_SEL(1,0) SEL(A:C) FB_SEL(1,0) VDDQA VDDQB
I, PU I, PU I, PU I, PD I, PD I, PD I, PD Supply Supply
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD
Notes 1. PU = Internal pull up, PD = Internal pull down 2. A 0.1-F bypass capacitor must be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristics is cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply pins.
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Table 1. Pin Definition - 52-Pin 1.0-mm TQFP package (Continued) Pin[1] 45, 49 28 13 12 15 1, 19, 24, 30, 35, 39, 43, 47, 51 27, 42 Name VDDQC VDDFB AVDD VDD AVSS VSS IO Supply Supply Supply Supply Supply Supply Type VDD VDD VDD VDD Ground Ground Description 2.5V or 3.3V Power supply for bank C output clocks[2,3] 2.5V or 3.3V Power supply for feedback output clock[2,3] 2.5V or 3.3V Power supply for PLL[2,3] 2.5V or 3.3V Power supply for core and inputs[2,3] Analog Ground Common Ground
NC
No Connection
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Table 2. Frequency Table Feedback Output Divider /8 /12 /16 /24 /32 /48 /4 /6 /8 /12 VCO Input Clock * 8 Input Clock * 12 Input Clock * 16 Input Clock * 24 Input Clock * 32 Input Clock * 48 Input Clock * 4 Input Clock * 6 Input Clock * 8 Input Clock * 12 Input Frequency Range (AVDD = 3.3V) 25 MHz to 62.5 MHz 16.6 MHz to 41.6 MHz 12.5 MHz to 31.25 MHz 8.3 MHz to 20.8 MHz 6.25 MHz to 15.625 MHz 4.2 MHz to 10.4 MHz 50 MHz to 125 MHz 33.3 MHz to 83.3 MHz 25 MHz to 62.5 MHz 16.6 MHz to 41.6 MHz Input Frequency Range (AVDD = 2.5V) 25 MHz to 50 MHz 16.6 MHz to 33.3 MHz 12.5 MHz to 25 MHz 8.3 MHz to 16.6 MHz 6.25 MHz to 12.5 MHz 4.2 MHz to 8.3 MHz 50 MHz to 100 MHz 33.3 MHz to 66.6 MHz 25 MHz to 50 MHz 16.6 MHz to 33.3 MHz
Table 3. Function Table (configuration controls) Control TCLK_SEL VCO_SEL0 VCO_SEL1 PLL_EN MR#/OE Default 0 0 0 1 1 0 TCLK0 VCO/2 (mid input frequency range) Gated by VCO_SEL0 1 TCLK1 VCO/4 (low input frequency range) VCO (high input frequency range)
Bypass mode, PLL disabled. The input clock connects PLL enabled. The VCO output connects to the output dividers to the output dividers Outputs disabled (three-state) and reset of the device. During reset/output disable the PLL feedback loop is open and the VCO running at its minimum frequency. The device is reset by the internal power on reset (POR) circuitry during power up. QA, QB, and QC outputs disabled in LOW state. FB_OUT is not affected by CLK_STP#. Outputs enabled
CLK_STP#
1
Outputs enabled
Table 4. Function Table (Bank A, B, and C) VCO_SEL1 0 0 0 0 1 1 VCO_SEL0 0 0 1 1 x x SELA 0 1 0 1 0 1 QA(4:0) /4 /8 /8 /16 /2 /4 SELB 0 1 0 1 0 1 QB(4:0) /4 /8 /8 /16 /2 /4 SELC 0 1 0 1 0 1 QC(3:0) /8 /12 /16 /24 /4 /6
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Table 5. Function Table (FB_OUT) VCO_SEL1 0 0 0 0 0 0 0 0 1 1 1 1 VCO_SEL0 0 0 0 0 1 1 1 1 x x x x FB_SEL1 0 0 1 1 0 0 1 1 0 0 1 1 FB_SEL0 0 1 0 1 0 1 0 1 0 1 0 1 FB_OUT /8 /16 /12 /24 /16 /32 /24 /48 /4 /8 /6 /12
Absolute Maximum Conditions
Parameter VDD VDD VIN VOUT VTT LU RPS TS TA TJ OJC OJA ESDH FIT Description DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch Up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Manufacturing test Functional Ripple Frequency < 100 kHz Non Functional Functional Functional Functional Functional Functional Relative to VSS Relative to VSS Condition Min -0.3 2.375 -0.3 -0.3 - 200 - -65 -40 - - - 2000 10 Max 5.5 3.465 VDD + 0.3 VDD + 0.3 VDD / 2 - 150 +150 +85 150 23 55 - Unit V V V V V mA mVp-p C C C C/W C/W Volts ppm
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DC Electrical Specifications (VDD= 3.3V 5%, TA = -40C to +85C)
Parameter VIL VIH VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Description Input Voltage, Low Input Voltage, High Output Voltage, Low
[4]
Condition LVCMOS LVCMOS IOL = 24 mA IOL = 12 mA IOH = -24 mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded at 100 MHz Outputs loaded at 200 MHz
Min - 2.0 - - 2.4 - - - - - - - 12
Typ. - - - - - - - 5 - 225 290 4 15
Max 0.8 VDD+0.3 0.55 0.30 - -100 100 10 1 - - - 18
Unit V V V
Output Voltage, High Input Current, Low
[5]
[4]
V A A mA mA mA
Input Current, High
[5]
PLL Supply Current Quiescent Supply Current Dynamic Supply Current
Input Pin Capacitance Output Impedance
pF
DC Electrical Specifications (VDD= 2.5V 5%, TA = -40C to +85C)
Parameter VIL VIH VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Description Input Voltage, Low Input Voltage, High Output Voltage, Output Voltage, Input Current, Input Current, Low[4] High[4] Condition LVCMOS LVCMOS IOL = 15 mA IOH = -15 mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded at 100 MHz Outputs loaded at 200 MHz Input Pin Capacitance Output Impedance Min - 1.7 - 1.8 - - - - - - - 14 Typ. - - - - - - 5 - 135 160 4 18 Max 0.7 VDD+0.3 0.6 - -100 100 10 1 - - - 22 pF Unit V V V V A A mA mA mA
Low[5] High[5]
PLL Supply Current Quiescent Supply Current Dynamic Supply Current
Notes 4. Driving one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 series terminated transmission lines. 5. Inputs have pull up or pull down resistors that affect the input current
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AC Electrical Specifications (VDD= 2.5V 5%, TA = -40C to +85C)
Parameter[6] fVCO fin Description VCO Frequency Input Frequency /4 Feedback /6 Feedback /8 Feedback /12 Feedback /16 Feedback /24 Feedback /32 Feedback /48 Feedback Bypass mode (PLL_EN = 0) frefDC tr , tf fMAX Input Duty Cycle TCLK Input Rise/FallTime Maximum Output Frequency 0.7V to 1.7V /2 Output /4 Output /6 Output /8 Output /12 Output /16 Output /24 Output DC tr , tf t() tsk(O) tsk(B) Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Bank-to-Bank Skew 0.7V to 1.8V TCLK to FB_IN, does not include jitter Skew within Bank Banks at same frequency Banks at different frequency tPLZ, HZ tPZL, ZH BW Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3 dB) Cycle-to-Cycle Jitter VCO_SEL = 0 VCO_SEL = 1 Same frequency Multiple frequencies tJIT(PER) tJIT() tLOCK Period Jitter IO Phase Jitter Maximum PLL Lock Time Condition Min 200 50 33.3 25 16.7 12.5 8.3 6.3 4.2 0 25 - 100 50 33.3 25 16.7 12.5 8.3 45 0.1 -100 - - - - - - - - - - - - Typ. - - - - - - - - - - - - - - - - - - - - - - - - - - - 0.5 - 1.0 1.0 - 2.0 - - - - - Max 400 100 66.6 50 33.3 25 16.7 12.5 8.3 200 75 1.0 200 100 66.6 50 33.3 25 16.7 55 1.0 100 150 150 225 10 10 - - 150 300 100 150 1 ps ps ms ps ns ns MHz % ns ps ps ps % ns MHz Unit MHz MHz
tJIT(CC)
Note 6. AC characteristics apply for parallel output termination of 50 to VTT. Parameters are guaranteed by characterization and are not 100% tested.
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AC Electrical Specifications (VDD= 3.3V 5%, TA = -40C to +85C)
Parameter[6] fVCO fin Description VCO Frequency Input Frequency /4 Feedback /6 Feedback /8 Feedback /12 Feedback /16 Feedback /24 Feedback /32 Feedback /48 Feedback Bypass mode (PLL_EN = 0) frefDC tr , tf fMAX Input Duty Cycle TCLK Input Rise/FallTime Maximum Output Frequency 0.8V to 2.0V /2 Output /4 Output /6 Output /8 Output /12 Output /16 Output /24 Output DC tr , tf t() tsk(O) tsk(B) Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Bank-to-Bank Skew 0.8V to 2.4V TCLK to FB_IN, same VDD, does not include jitter Skew within Bank Banks at same voltage, same frequency Banks at same voltage, different frequency Banks at different voltage tPLZ, HZ tPZL, ZH BW Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3dB) Cycle-to-Cycle Jitter VCO_SEL = 0 VCO_SEL = 1 Same frequency Multiple frequencies tJIT(PER) tJIT() tLOCK Period Jitter IO Phase Jitter Maximum PLL Lock Time IO at same VDD Condition Min 200 50 33.3 25 16.7 12.5 8.3 6.3 4.2 0 25 - 100 50 33.3 25 16.7 12.5 8.3 45 0.1 -100 - - - - - - - - - - - - - Typ. - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0.5 - 1.0 1.0 - 2.0 - - - - - Max 500 125 83.3 62.5 41.6 31.3 20.8 15.6 10.4 200 75 1.0 200 125 83.3 62.5 41.6 31.3 20.8 55 1.0 100 150 150 225 250 10 10 - - 150 300 100 150 1 ps ps ms ps ns ns MHz % ns ps ps ps % ns MHz Unit MHz MHz
tJIT(CC)
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Figure 2. AC Test Reference for VDD = 3.3V / 2.5V
Pulse Generator Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 3. Propagation Delay t(), Static Phase Offset
LVCMOS_CLK
VDD VDD/2 GND VDD
FB_IN
VDD/2
t()
GND
Figure 4. Output Duty Cycle (DC)
VDD VDD/2
tP
T0
GND
DC = tP / T0 x 100%
Figure 5. Output-to-Output Skew, tsk(O)
VDD VDD/2 GND VDD VDD/2
tSK(O)
GND
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Ordering Information
Part Number CY29775AI CY29775AIT Pb-free CY29775AXI CY29775AXIT 52-pin TQFP 52-pin TQFP -Tape and Reel Industrial, -40C to +85C Industrial, -40C to 85C Active Active 52-pin TQFP 52-pin TQFP -Tape and Reel Package Type Product Flow Industrial, -40C to +85C Industrial, -40C to 85C Status Obsolete Obsolete
Package Drawing and Dimension
Figure 6. 52-Lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B
51-85158-**
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Document History Page
Document Title:CY29775 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Document #: 38-07480 Rev. ** *A ECN No. 125955 1875214 Issue Date 04/29/03 See ECN Orig. of Change RGL New Data Sheet Description of Change
WWZ/AESA Added Pb-free part numbers and updated device status
(c) Cypress Semiconductor Corporation, 2003-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07480 Rev. *A
Revised December 19, 2007
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Spread Aware is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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